Transmission Line Design on Silicon

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Contents

What are we going to look at?

  • Passive structures over silicon
  • Propagation modes on transmission lines
  • Microstrip vs. CPW
  • Field structure
  • Attenuation

Passive Structures on Silicon

Caption
  • We have many metal layers that could be used to implement passive structures like transmission lines, inductors
  • Can implement transmission lines using microstrip, coplanar waveguides, slotlines, etc.
  • Considerations in chosing metal layer and type of transmission line:
    • Attenuation (due to ohmic losses, and substrate losses)
    • Characteristic impedance (Zo)
    • Dimensions

Transmission Lines on Silicon

Measured insertion loss of four 50 Ohm transmission lines using the top metal layer (1 um thick) on a CMOS process.

The type of transmission line used will have a significant effect on the behaviour of the line. See, for example, the variation in insertion loss of four different 50 Ohm transmission lines on silicon, all implemented using the top metal layer.

  • Microstrip line: upper signal conductor, lower ground plane
  • CPW: upper signal conductor, coplanar ground planes, possibly lower ground plane
  • Question: how to these compare in terms of attenuation, Zo, and dimensions?
  • Need to find ways of expressing these quantities, and how the signals propagate
  • Do we need to use a metal layer as a ground plane to shield the signal from the silicon substrate?
Microstrip
CPW



Metal-insulator-semiconductor (MIS) transmission lines

Caption
  • Model transmission line as lumped element model: Rs: series ohmic resistance, Rl: longitudinal current flow in substrate, CSG: capacitance between the signal line and the coplanar grounds, CSSi: capacitance between signal and substrate, CSi: displacement current flow in the substrate, GSi: perpendicular current flow in the substrate. All in per unit length.
  • Provided that the skin depth at the frequency of interest is more than the thickness of the metal, we can find the ohmic resistance Rs using the resistance of the metal layer given for a process (usually given in ohms per square, \Omega/\Box), R_s = \frac{R_\Box}{W} where W is the width of the central conductor.
  • Coplanar ground planes are assumed to be infinitely wide so their current densities are much lower, and their resistance is negligible compared to the central conductor.
  • When the skin effect is significant, we have to modify the effective resistance per unit square:
    • In general, the resistance per square can be found from the material resistivity by R_\Box = \frac{\rho}{t} where t is the thickness of the metal
    • When skin depth is less than half the metal thickness, we can simply use t = δ to find the equivalent resistance per unit square, where \delta = \frac{1}{\sqrt{f \pi \mu_o \sigma_s}} is the skin depth and σs is the conductivity of the metal
  • Rl models the longitudinal current flow in the substrate underneath the signal line
  • If we know the depth of field penetration into the semiconductor d and the width of the field penetration w, we can estimate the equivalent resistance per unit length of the substrate: R_l =\frac{\rho_s}{wd}, ρs = 1 / σs.
  • Since the depth is usually determined by the skin depth, and since the width of the field w is approximately the same as the width of the signal line W, we get R_l \approx \frac{\rho_s}{\delta_s W}, where δs is the skin depth of silicon and W is the width of the signal line (see Kwon, Quasi-TEM Analysis of "slow-wave" mode propagation on Coplanar Microstructure MIS Transmission Lines).
  • Modeling the lateral current flow is more complex: using conformal mapping, GSi = 2σsF, F=\frac{K(k')}{K(k)}, with K(k) being the complete elliptic integral of the first kind, and
k = \frac{W}{W+2S}
k'=\sqrt{1-k^2}
  • Note: In Kwon's paper he has W and S switched from our definition
  • The effective substrate capacitance CSi = 2εsF, where εs is the permittivity of the substrate εoεr, (where εr is around 11.9 for silicon), and F is as above
  • The capacitance to the substrate CSSi can be calculated using the standard parallel plate equation:
C_{SSi} = \epsilon_d \frac{W}{h} K

where εd is the relative permittivity of the interlayer dielectrics, h is the height of the signal line above the substrate, and K a number slightly greater than one that accounts for fringing (this is often ignored for simple analyses)

  • The last capacitance, CSG, can be calculation by observing that as \omega\rightarrow \infty, the equivalent capacitance of the three capacitors has to equal the total capacitance C of the transmission line, or
C_{SG} = C - \frac{C_{SSi} C_{Si}}{C_{SSi} + C_{Si}}
  • It only remains now to calculate the effective total inductance per unit length L and capacitance per unit length C.
  • This can be calculated using a field solver, or if we know the characteristic impedance Zo and phase velocity v of a signal on the transmission line, then
L = \frac{Z_o}{v}
C = \frac{1}{Z_o v}

Metal-insulator-semiconductor (MIS) transmission line simulations

  • Simulations of the potiential (contour lines) and electron concentration (colourmap) for GaAs and silicon substrates
  • Notice: silicon substrate is behaving like a metal - potential goes to zero at its surface, little field penetrates
  • Very little electron redistribution due to fields (like a metal) since little electric field penetration
50 Ohm CPW line (W=20 um, G=2.5 um) above GaAs substrate
50 Ohm CPW line (W=20 um, G=2.5 um) above silicon substrate
  • A finite different simulator was used to simulate the performance of a 50 Ω transmission line, and compare it to measured results
Comparison of E field intensity (in V/m) and H field intensity (in A/m) in GaAs and Si along bisecting plane.
Comparison of simulated and measured attenuation for a 50 Ohm CPW transmission line with a central conductor width of W=20 um and a gap of S=2.5 um.

Design of Microstrip Transmission Lines

  • Need to minimize losses
  • Use of top metal layer minimizes the capacitance to the substrate, and minimizes attenuation
  • Other option: use lower metal layer as a ground plane to ``shield the signal from the semiconductor substate
  • However - we need to consider the characteristic impedance

Microstrip transmission line εe and Zo

  • εe often given by
\epsilon_e = \frac{\epsilon_r + 1}{2} + \frac{\epsilon_r -1}{2}\frac{1}{\sqrt{1+12 t /W}}

where t is the substrate thickness and W is the width of the upper conductor

  • From this equation for εe,
Z_o = \begin{cases} \frac{60}{\epsilon_e} \ln \bigg(\frac{8t}{W} + \frac{W}{4t} \bigg) & W/t \le 1 \\ \frac{120 \pi}{\sqrt{\epsilon_e} \bigg(W/t + 1.393 + 0.667 \ln (W/t + 1.444) \bigg)} & W/t \ge 1 \end{cases}
  • See Pozar for more information on these equations
  • If we desire a specific Zo for the transmission line, the ratio W / t may be found by rearranging the above expression to give
\frac{W}{t} = \begin{cases} \frac{8 e^A}{e^{2A} -2} &W/t < 2, \\ \frac{2}{\pi} \bigg(B-1-\ln(2B-1) +<br> \frac{\epsilon_r -1}{2 \epsilon_r} \bigg[\ln(B-1) + 0.39 - \frac{0.1}{\epsilon_r} \bigg] \bigg) & W/t > 2 \end{cases}

where

A = \frac{Z_o}{60} \sqrt{\frac{\epsilon_r + 1}{2}} + \frac{\epsilon_r -1}{\epsilon_r + 1} \bigg(0.23 + \frac{0.11}{\epsilon_r} \bigg)
B = \frac{377 \pi}{2 Z_o \sqrt{\epsilon_r}}

Microstrip transmission line impedances in CMOS

  • If we desire Zo = 50 Ω for the transmission line and require that the dielectric thickness t be less than 7 μm, using the equations for impedances results in a width W of approximately 14 μm
  • Producing a higher impedance results in a narrower transmission line, and more attenuation
  • Difficult to make high impedance line without it having large attenuation
  • Also becomes a challenge if it has to carry significant current - process rules limit current density on transmission lines

Design of Coplanar waveguides

Caption
  • Coplanar waveguides use coplanar ground conductors
  • Typical equations for CPWs assume no underlying ground plane. E.g. expressions for Zo, εe, etc. are empirical expressions from measured data (e.g. I. Bahl and P. Bhartia, Microwave Solid State Circuit Design, John Wiley & Sons, 1988.)
  • Elliptic integral K(k) must be solved in order to find these values. This is best done using Scilab or MATLAB (MATLAB: "ellipke" function, Scilab: "delip" function)
  • εe given by
\epsilon_e = 1 + \frac{\epsilon_r -1}{2} \frac{K(k') K(k_1)}{K(k) K(k_1')}

CPW characteristic impedance

  • Zo given by
Z_o = \frac{30 \pi}{\sqrt{\epsilon_e}} \frac{K(k')}{K(k)}

where

k= \frac{W}{W+2S}
k_1 = \frac{\sinh (\pi W / 2 h)}{\sinh (\pi (W+2S) / 2 h)}
k' = \sqrt{1-k^2}
  • The elliptic integral K(k) is
K(k) = \int_0^1 \frac{dx}{\sqrt{(1-x^2)(1-k^2 x^2)}}
  • If we desire Zo = 50 Ω for the transmission line, and if the dielectric thickness t is 7 μm, using the equations for impedances results in a width W of approximately 20 μm for a gap of 2.5 μm
  • Producing a higher impedance results in a narrower transmission line, and more attenuation. Because of this, it is difficult to make high impedance lines without large attenuation. It also becomes a challenge if it has to carry significant current, as process rules limit current density on transmission lines

Attenuation of CPW with varying geometries

Simulated attenuation for 50 Ohm MIS CPW lines: W=5 um, S=0.5 um
W=10 um, S=1.5 um
W=15, S=2 um
W=25, S=4 um

Simulated CPW attenuation using aluminum or copper transmission lines

Identical 50 Ohm CPW transmission lines with W=20 um using copper vs. aluminum (copper's conductivity is around double that of aluminum

Stacked Left Handed Transmission Lines in CMOS Technology


Feasibility Seminar by Symon Podilchak, 03/07/2006

LTCC Implementation
Possible One Unit Structure
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