Introduction to LNA Design

From BMF Wiki

Motivation

LNAs are used at the input of wireless receivers.

Wireless receivers need to be able to detect and amplify incoming low-power signals without adding much noise. The most common solution uses low noise amplifiers (LNAs) as the first stage. To design LNAs, we need to know how to minimize the noise figure of an amplifier. We will look at the noise properties of two port devices, and how we can use the Smith chart to help in the design. We will design a MOSFET LNA for gain and low noise

Note that this section assumes familiarity with matching. If you are not comfortable with impedance matching, you may review Impedance Matching and the Smith Chart and L-section Matching Networks.

References:
- Pozar p. 214--218
- Lee ch. 10, 11
- Gonzalez p. 299--323

Noise Figure of a Two-Port Device

Remember: noise factor of a two port device is the ratio of the signal-to-noise ratio at the input to that at the output is the noise factor, or noise figure if given in dB

$F = \frac{\frac{S_i}{N_i}}{\frac{S_o}{N_o}} = \frac{1}{G} \frac{N_o}{N_i} = L \frac{N_o}{N_i}$

where $G$ is the gain of the device and $L$ is the loss of the device

$G$ would be used for an amplifier, $L$ would be used for a lossy element

It can be expressed as a function of the properties of the device as:

$F = F_{min} + \frac{R_N}{G_s} |Y_s - Y_{opt}|^2$

where $Y s = G s + j B s = 1 / Z s$ is the source admittance presented to the transistor, $Y o p t = G o p t + j B o p t$ is the optimum source admittance, $F m i n$ is the minimum noise figure of the device, which is attained when $Y s = Y o p t$ . $R N$ is the equivalent noise resistance of the transistor, and $G s$ is the real part of the source admittance.

Four parameters required to characterize any two port device at given frequency, temperature and bias ( $F m i n$ , $R N$ , $G o p t$ , and $B o p t$ )
Noise figure is only a function of 'input' matching network (unless output matching network is lossy)
$R N$ shows how quickly the noise figure increases for $Y_s \neq Y_{opt}$ , i.e. how sensitive the device is to input admittance

Practical Noise Figure Measurement (Y-Factor)

The noise figure of a device is usually measured by applying two different noise powers to the input and examining the output powers $N 1$ and $N 2$

Measuring the noise figure of a device.

For a device with gain $G$ , the noise outputs are

N 1 = G k T 1 B + G k T e B

N 2 = G k T 2 B + G k T e B

where $N 1$ and $N 2$ are the output noise powers when the noise source is at a physical temperature of $T 1$ and $T 2$ , respectively, assuming the DUT is impedance matched to the noise source, and $T 1 > T 2$

We set $T 1$ and $T 2$ (e.g. by changing the physical temperature of a resistor), and can measure $N 1$ and $N 2$
Input and output must be matched (i.e. same impedance)
Define $Y=\frac{N_1}{N_2}$ , and then the device noise temperature is

$T_e = \frac{T_1 - Y T_2}{Y-1}$

Agilent E4446A spectrum analyzer with noise measurement capability.

Noise figure is related to equivalent noise temperature by

$F = \frac{S_i N_o}{S_o N_i} = \frac{S_i kGB(T_o + T_e)}{GS_i k T_o B} = 1 + \frac{T_e}{T_o}$ where $T o$ is system temperature, and $T e$ is noise temperature

We use this approach to measure the four noise parameters. $F m i n$ is determined by varying the source admittance seen by the device under test, and finding the minimum measured noise figure. $Y o p t = G o p t + j B o p t$ is the value of $Y s$ that results in $F = F m i n$ . $R n$ is the last unknown, and is solved by using muliple measured sets of data for $F m i n$ and $Y o p t$ .

Noise analyzers are available to do these measurements, and they are built in to some spectrum analyzers, like the one shown on the right. More detail about noise measurement is available in Fundamentals of RF and Microwave Noise Figure Measurement, from Agilent, 2000.

Expressions for MOSFET Noise Parameters

We can design an LNA using an equivalent noise model like one shown below (similar to small-signal model)

Equivalent noise model of a MOSFET

Noise model becomes complex at high frequencies, so we can also design for low noise using noise parameters $F m i n$ , $R n$ , and $Y o p t = G o p t + j B o p t$ which can be either derived from the equivalent circuit model, or measured (more accurate)
Useful to be able to calculate noise parameters from noise model, and vice versa
We can do this by finding equivalent input noise voltage and current sources, so that all noise is reflected to the input of the transistor as shown below, rather than incorporated inside of it in a noise model

Input referred noise model

We will ignore $1 / f$ noise to simplify the results, since for LNA design the $1 / f$ noise is not significant at RF/microwave frequencies
We will examine the derivation of noise figure parameters in our discussion of Noise_in_MOSFETs_and_HBTs; some simple expressions for the parameters are:

$R_n = \frac{\overline{v_i^2}}{4kT\Delta f} = \frac{\gamma g_{d0}}{g_m^2}$

$B_{opt} = -Y_c = -j \omega C_{gs} \left(1 + \frac{g_m}{g_{d0}} |c| \sqrt{\frac{\delta}{5 \gamma}}\right)$

$G_{opt} = \sqrt{\frac{G_u}{R_n} + \Re(Y_c)^2} = \sqrt{\frac{G_u}{R_n}} = \omega C_{gs} \frac{g_m}{g_{d0}} \sqrt{\frac{\delta}{5 \gamma} (1-|c|^2)}$

$F = F_{min} = 1 + 2R_n(G_{opt} + G_c) \approx 1 + \frac{2}{\sqrt{5}} \frac{\omega}{\omega_T} \sqrt{\gamma \delta(1-|c|^2)}$

where $\alpha = \frac{g_m}{g_{d0}}$ , $g d 0$ is the drain-source conductance at $V D S = 0$ , $c\approx j0.395$ for long-channel MOSFETs, $δ$ is the gate noise parameter $\approx 4/3$ for long-channel devices, and $γ$ is the drain noise parameter between 2/3 and 1.

For more information, see Lee, p. 248

MOSFET Noise Parameter Observations

$F m i n$ goes up considerably for $ω > ω T$
Since $γ$ and $δ$ both increase with decreasing channel length, short channel devices would have increasing noise figure except that $ω T$ scales with decreasing channel length as well
The imaginary part of the admittance seen at the input of the MOSFET implies that the MOSFET needs to see an inductive element for minimum noise
The real part of the admittance at the input of the MOSFET needs to be $\approx \omega C_{gs}$ for minimum noise
Now that we know all the noise parameters we can calculate the noise figure for any source admittance using the equation

$F = F_{min} + \frac{R_n}{G_s} | Y_s - Y_{opt} |^2$

Input noise and power match

For low noise figure, we want $Y s = Y o p t$ , ( $Γ s = Γ o p t$ ) i.e. noise match, where $Y o p t$ is the source admittance that gives $F = F m i n$
For good gain and input match, want $Y_s = Y_{in}^*$ ( $\Gamma_s = \Gamma_{in}^*$ ), i.e. impedance match
Can compromise, and select $Γ s$ somewhere between $Γ o p t$ and $\Gamma_{in}^*$ (as long as it is in the stable region of $Γ s$ )
Noise is not a function of output match, so we usually try to conjugately match the output, i.e. $\Gamma_{L}=\Gamma_{out}^*$ .

Available gain, noise, and source stability circles for a MOSFET.

Matching Network Design Compromising Gain and Noise

In order to properly design an LNA,we need to know:
- How much does gain go down as $Γ S$ moves away from $\Gamma_{in}^*$ ?
- How much does noise go up as $Γ S$ moves away from $\Gamma_{opt}^*$ ?

Gain Circles

To find how gain varies with $Γ S$ , we can use the available power gain equation to find available power gain circles in the $Γ s$ plane (shown in cyan). Available power gain is the ratio of power available from the amplifier to to that available from the source, and so is a function of the input matching network. The available power gain is defined as:

$G_a = \frac{P_{avn}}{P_{avs}} = \frac{1}{1 - |\Gamma_{out}|^2} |S_{21}|^2 \frac{1-|\Gamma_S|^2}{(1-\Gamma_S S_{11})^2}$

where

$\Gamma_{out} = S_{22} + \frac{S_{21}S_{12}\Gamma_S}{1-S_{11} \Gamma_S}$

This can be rearranged to yield equations that provide the centre and radii of constant gain circles. These equations are best solved by computer, as they are cumbersome to work with by hand. For more information on gain circles, see Gonzalez, or Orfanidis, Electromagnetic Waves and Antennas, p. 445

Associated gain

Associated gain of a transistor is a useful figure of merit when designing low noise amplifiers. It is equal to the gain of the transistor under the conditions that:
- The input of the transistor sees the optimum reflection coefficient for low noise, i.e. $Γ s = Γ o p t$
- The output of the transistor is terminated in a conjugate match, i.e. $\Gamma_L = \Gamma_{out}^*$
$Γ o u t$ is set by $Γ s = Γ o p t$ , since

$\Gamma_{out} = S_{22} + \frac{S_{12} S_{21} \Gamma_{opt}}{1 - S_{11} \Gamma_{opt}}$

Noise circles

We can rearrange the noise figure equation to show that the circles (shown in blue) of constant noise factor $F$ (as ratio, not in dB) are given by center and radius of

$C_F = \frac{\Gamma_{opt}}{N+1}$

$R_F = \frac{\sqrt{N(N+1 - |\Gamma_{opt}|^2)}}{N+1}$

where the noise figure parameter is $N = \frac{F - F_{min}}{4 R_N/Z_o} |1+\Gamma_{opt}|^2$

Limitations of designing LNAs this way

We can use this technique to design a matching network that gives a compromise between gain, impedance match, and noise. However, it often results in an LNA that has poorer performance than necessary. In the next section we will see how adding a couple of other components can improve the behaviour.

LNA Topologies Compared

Inductive degeneration used for noise and impedance matching.

Let's look at some common methods of designing LNA's, three of which use inductive degeneration
Inductive degeneration can be used to move $Γ i n$ closer to the centre of the Smith chart (i.e. it is used for matching)
Inductive degeneration can be used in conjunction with transistor sizing to move $Γ o p t$ and $Γ i n$ closer together, making it possible to achive low noise figure, high gain, and good input match all at the same time.
More detail is available from CMOS Low-Noise Amplifier Design Optimization Techniques, (T. Nguyen et al., IEEE)

LNA Design Method	Pro	Con	Schematic
Conjugate noise match (CNM)	$F = F m i n$ , simple	Poor impedance match
Simultaneous noise and impedance match (SNIM)	$F = F m i n$ , good impedance match	$\uparrow$ power
Power constrained noise optimization (PCNO)	Good impedance	$F > F m i n$
Power constrained SNIM (PCSNIM)	$F = F m i n$ , good impedance match	$\downarrow f_T$ , $\uparrow R_n$

LNA Design Flowchart

LNA Design methods

In many cases a cascode configuration is used, so a common gate MOSFET is added above the common source MOSFET. This improves the isolation between the input and output of the LNA, which simplifies matching. It also improves the gain, though at the expense of power consumption and noise.

Cascode configuration for an LNA.

The topologies here differ only in the degeneration used and extra capacitance in parallel with $C g s$ .
The first one (CNM) is very simple - a matching network is designed so that $Y s = Y o p t$ , and no degeneration is used.
The other three are just slightly different methods of using inductive degeneration

Biasing and device sizing for gain and noise

MOSFET noise and gain are functions of bias conditions and device size
A drain current density of approximately 0.25 mA/um gate width yields highest $f M A X$ and $f T$ , while 0.13 mA/um gate width yields lowest noise figure. For more information, see S. Voinigescu et al., A Comparison of Si CMOS, SiGe BiCMOS, and InP HBT Technologies for High-Speed and Millimeter-Wave ICs, SiRF
Generally shorter finger widths lead to higher $f M A X$ (until the width is small enough that the gate resistance is less than other parasitic resistances). E.g., for 0.13 um CMOS processes, a finger width of close to 1 um is best. See C. Doan et al., Millimeter-Wave CMOS Circuit Design, IEEE JSSC, Jan 2005, 144-155.

Design using Simultaneous Noise and Impedance Match (SNIM)

Inductive degeneration for an LNA.

Simple small-signal analysis of the circuit below gives that

$Z_{in}' = \frac{1}{Y_{in}'} = \frac{L_s g_m}{C_{gs}} + j \omega L_s - \frac{j}{\omega C_{gs}} = R + jX$

Real part: If we set $\frac{L_s g_m}{C_{gs}} =Z_o$ , we will have the input resistance equal to our source resistance.

Imaginary part: we would like this to be zero, so $\omega L_s = \frac{1}{\omega C_{gs}}$ , but since $L s$ is picked according to $\frac{L_s g_m}{C_{gs}}$ above , and $C g s$ is set by the device size, so the imaginary terms rarely happen to cancel.

We can add another degree of freedom by putting a small gate inductor $L g$ in series with the gate. In this case the input impedance becomes

$Z_{in} = \frac{1}{Y_{in}} = j \omega L_g + \frac{L_s g_m}{C_{gs}} + j \omega L_s - \frac{j}{\omega C_{gs}} = R + jX$

The imaginary part is set to zero when

$\omega (L_g + L_s) = \frac{1}{\omega C_{gs}}$

so we pick $L g$ to satisfy that equation.

Selecting these inductors provides a power match, and also can provide a noise match.

Adding the inductors resonates out Cgs, and sets $B o p t = 0$ . However, it doesn't affect $G o p t$ . If we pick our transistor size to make the real part of our optimum input admittance equal to the source admittance (i.e. $G_{opt} = Y_o=\frac{1}{Z_o}$ ) then the optimum source admittance for noise will be the same as that for power, and we will have simultaneous noise and impedance matching (hence the name of the method!)

Hence from above, we want

$G_{opt} \approx \alpha \omega C_{gs} \sqrt{\frac{\delta}{5 \gamma}(1-|c|^2)} = \frac{1}{Z_o}$

Example: MOSFET LNA design using SNIM

E.g. design an LNA for 10 GHz operation, using typical values of $γ = 2$ , $δ = 4$ , $| c | = 0.395$ , and $α = 0.85$ and a 50 $Ω$ source impedance
With these values, the equation for $G_{opt} \approx \alpha \omega C_{gs} \sqrt{\frac{\delta}{5 \gamma}(1-|c|^2)}$ reduces to

$C_{gs} \approx \frac{2G_{opt}}{\omega}$

and since we want $G o p t = 1 / 50 = 0.02$ , that means $C_{gs} \approx 0.64$ pF.

We need to determine the size of the device to achieve the required C_gs
- We can use a simple approximation to get an approximate size: For a MOSFET in saturation, $C_{gs} \approx \frac{2}{3} C_{ox}$ and $C_{ox} = \frac{\epsilon_{ox} \epsilon_o WL}{t_{ox}}$ - we can relate the required $C g s$ to device size by solving to give $W =\frac{3}{2} \frac{C_{gs} t_{ox}}{\epsilon_{ox} \epsilon_o L}$ .
- HOWEVER, remember that $C g s$ is only one of the capacitances at the gate of a MOSFET (others include the overlap capacitance and gate-to-diffusion sidewall capacitance). Calculating the required device width using only $C g s$ may result in a device that is double the necessary size. It is wise to use the previous step to estimate the device size, then simulate the true input capacitance of the device using the imaginary part of the input impedance (using S11).
For an $L = 0.18$ $μ$ m MOSFET with $t o x = 4$ nm and $ε o x = 3.7$ , a $C g s$ of 0.64 pF corresponds to a device with a total gate width of 650 $μ$ m
A single transistor this wide would have a very large equivalent gate resistance, so it is usually broken up into many parallel transistors with smaller gate resistance
Instead of using a single device with a gate width of 650 $μ$ m, we would use many short gate fingers in parallel: e.g. for 4 $μ$ m wide fingers we would need $650/4 \approx 162$ of them in parallel

Large width FET broken into many smaller fingers to reduce gate resistance.

We can then chose the $L s$ to give an input impedance of 50 $Ω$ using $\frac{g_m}{C_{gs}L_s}=Z_o$ once we have determined the device $g m$ at the particular bias condition. e.g. if $g m = 80$ mA/V at the bias conditions, $L_s = \frac{C_{gs} Z_o}{g_m}= 0.4$ nH.
Finally, the $L g$ can be added to set the imaginary part of the input impedance equal to zero, so $j \omega L_g + j \omega L_s = \frac{j}{\omega C_{gs}}$ . In this example, it turns out that $L g$ is not necessary, since $j \omega L_g \approx \frac{j}{\omega C_{gs}}$
Q: what important parasitic capacitance has this analysis ignored? What effect might it have on our results?
We have neglected the Miller capacitance C_gd, which makes up a significant portion of the input capacitance in short-channel MOSFETs. This can result in error in inductor sizes by a factor of 2 or 3. However, incorporating C_gd into the analysis complicates the expressions, so we often ignore it for the paper design, but when doing the simulations:
- Set the size of the source degeneration inductor so that $S 11$ lies along the r=1 circle
- Set the size of the gate inductor so that $S 11$ passes through the centre of the Smith chart at the design frequency.
- See design LNA_SNIM_10GHz in the ELEC853-2006 Cadence library.
HOWEVER: this method gives an extremely large device, with very large power consumption, usually impractical

MOSFET LNA design using Power Constrained Noise Optimization (PCNO)

We'd like to find a way to design for low noise while keeping our transistor width relatively small, which makes for low power consumption
The problem with the previous method (SNIM) was that we had to select $C g s$ according to

$C_{gs} \approx \frac{2G_{opt}}{\omega} = \frac{2}{Z_o \omega}$

which means a large width device $W =\frac{3}{2} \frac{C_{gs} t_{ox}}{\epsilon_{ox} \epsilon_o L}$

PCNO LNA topology.

Another option is to pick the transistor size we want to work with (which sets $C g s$ to a fairly small value), then simply find the minimum noise figure it can take on: this is the power constrained noise optimization (PCNO) method.
To do this, we choose the width using

$W_{opt,P}=\frac{3}{2} \frac{1}{\omega L C'_{ox} R_s Q_{sP}}$

where $C' o x$ is the oxide capacitance per unit area, $R s$ is the source resistance (usually 50 Ohms), and $Q_{sP}=\frac{1}{\omega C_{gs} R_s}$ is a parameter that can be optimized as a function of power to determine the device size. From Lee p. 382, $Q_{sP,opt} \approx 4.5$ for most device sizes that we would use for LNA's, giving

$W_{opt,P}=\frac{1}{3 \omega L C'_{ox} R_s}$

as the optimum width.

For more detailed information, see Shaeffer, IEEE JSSC, May 1997
Downside: This method does not generally provide $F = F m i n$ . We will not devote much time to it

MOSFET LNA design when power constrained (PCSNIM)

PCSNIM LNA topology.

We'd like to find a way to design for minimum noise figure while keeping our transistor width relatively small, which makes for low power consumption
Go back to SNIM: we had to select $C g s$ according to

$C_{gs} \approx \frac{2G_{opt}}{\omega} = \frac{2}{Z_o \omega}$

which means a large width device $W =\frac{3}{2} \frac{C_{gs} t_{ox}}{\epsilon_{ox} \epsilon_o L}$

Another option is to pick the transistor size we want to work with (which sets $C g s$ to a fairly small value), then simply add an extra capacitor $C e x$ between the gate and source to satisfy the noise conditions, i.e.

$C_{gs} + C_{ex} \approx \frac{2G_{opt}}{\omega} = \frac{2}{Z_o \omega}$

'what will happen to the $f T$ and $f M A X$ of the transistor? What conclusions can we draw about the frequency range over which this method is useful?'
Procedure:
- Use the value of $V G S$ that results in lowest $F m i n$ (usually this sets the current density to around 0.13 mA/um)
- Choose the transistor size $W$ according to current disspation or power consumption restrictions and measure, simulate, or calculate $C g s$
- Pick $C e x$ and $L s$ to satisfy

$C_{gs} + C_{ex} \approx \frac{2G_{opt}}{\omega} = \frac{2}{Z_o \omega}$

$\frac {L_s g_m}{C_{gs} + C_{ex}} =Z_o$

$j \omega (L_s + L_g) - \frac{j}{\omega (C_{gs} + C_{ex})} = 0$

The numbers calculated using the analytical approach can be used as starting points for simulations. See design LNA_PCSNIM_10GHz in the ELEC853-2006 Cadence library. Simulated results for it are shown below.

Simulated input match and noise for 10 GHz LNA designed using PCSNIM method in 0.18 um CMOS. Current consumption is about 10 mA.

Noise figure bandwith decreases with decreasing device size. Source: Nguyen, IEEE MTT May 2004

.

As we shrink the transistor to have smaller power dissipation, the noise resistance $R N$ increases, so the transistor is very sensitive to input impedance changes, and we get a very narrow bandwidth over which the noise figure is low

Load matching network design

Chosing the load matching network for an LNA.

The load network does not affect noise (as long as it is lossless), so we usually design it last. We need first to find $Γ o u t$ with the source matching network in place, and plot the load side stability circle (denoted LSB in the Direct Plot Form of Analog Environment).

If $\Gamma_{out}^*$ is in the stable region, picking $\Gamma_s = \Gamma_{out}^*$ will achieve highest gain and best output power match. Otherwise, we need to either stabilize the transistor by adding a resistor at the output (described in the ELEC-483 notes on stabilizing a transistor), or pick $Γ L$ somewhere in the stable region. In this case it is best to plot operating power gain circles that show how the overall gain will decrease as $Γ L$ moves away from $\Gamma_{out}^*$ , similar to how it was done for the source. These circles are best plotted by computer, as the equations are complex.

Inserting the output matching network may slightly change the input match, often requiring that the input be re-tuned. This interative process can be simplified by using a cascode structure, as the common gate stage isolates the output from the input.

Comparison of LNA Topologies

A Comparison of the Performance of LNA Topologies for the cascode configuration at various frequencies shows the advantages and disadvantages of the four types. Also see the [1] four types compared on a spreadsheet.

A comparison of the performance of LNA topologies using a common source MOSFET is also available for a range of frequencies from 1 - 20 GHz.